Informatics Publishing Limited

S. Nandhini ¹, R. Satyabama ²

Affiliations
1 VLSI Design, Government College of Technology, Coimbatore, IN
2 ECE Department, Government College of Technology, Coimbatore, IN

Abstract

Quantum Cellular Automata (QCA) is perfect replacement of Complementary Metal Oxide Semiconductor (CMOS) technology for digital designs.  As transistors decrease in size to accommodate in a single die, it increases chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit. It can be implemented by using reversible gates which will not dissipate power during computation. In general, the testing of sequential circuits is difficult as compared to combinational circuits since it need to test along with the previous state. In this paper, the sequential circuit based on reversible logic can be tested using only two test vector, thereby eliminating the need for any type of scan-path access to internal memory cells. The two test vectors are all 1s and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. Along with that a new design for multiplexer is implemented based on conservative QCA logic, that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors.

Keywords

Quantum-Dot Cellular Automata, Fredkin Gate, Reversible Logic, Double Edge Triggered Flipflop, MX-Cqca.

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A. Nithya ¹, R. Satyabama ¹

Affiliations
1 Department of Electronics & Communication Engineering, Government College of Technology, Coimbatore, IN

Abstract

Carry Select Adder is known to be the fastest adder among the conventional adder structure. Due to rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has been developed by identifying the redundant logic operation and data dependence of the Conventional Carry Select Adder and Binary To Excess One Converter. In the proposed CSLA scheme the redundant logic operations present in the conventional CSLA are eliminated. Carry Selection operation is scheduled before the calculation of the final sum. Bit pattern of two anticipating Carry words (corresponding to cin=0 and 1) and fixed cin bits are used for logic optimization of Carry Select and generation unit. An efficient CSLA design is obtained using optimized logic unit. The proposed Carry Select Adder scheme is designed and implemented in cadence RC Encounter 180nm technology. Synthesis result shows that the proposed CSLA design involves 53% less area and consumes 50% less energy than Conventional CSLA and also the proposed CSLA design involves 20% less area and consumes 37% less energy than the BEC based CSLA on average, for different bit-widths.

Keywords

Redundant Logic, Data Dependence, Carry Select Adder (Csla), Binary to Excess One Converter (BEC).

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